RISC-V

Great technological displacement germinates in the accumulating deficiencies of the incumbent order. For over three decades, computing consolidated around two monolithic architectures: x86, a vertically integrated duopoly whose CISC legacy imposed a constant power and die-area tax for backwards compatibility, and ARM, a horizontal licensing model that, despite its RISC origins, evolved its own complexity creep and erected formidable multi-million dollar IP barriers.
Innovation was channeled through a narrow gate with a steep cover charge.

Into this solidified order stepped a small team at UC Berkeley in 2010, motivated by frustration over the lack of a free, open, and non-trivial baseline ISA for research. RISC-V was conceived as a short-term project whose revolutionary potential lies not in a single performance breakthrough but in elegant, composable modularity: a frozen base integer set coupled with standard extensions, forming a Lego-like processor construction kit enabling a single binary to span from microcontroller to server.

Part I traces RISC's intellectual history and provides a technical taxonomy of RISC-V, explaining how its design solves the paradox of a stable software target free for radical hardware exploration. The central drama is how that openness became the mechanism for a new kind of capture. The early Western landscape, dominated by academia and startups like SiFive, was built on academic core generators like Rocket and BOOM-research platforms, not industrial products. The crucial distinction lies between an open standard, the ISA specification, and an open-source implementation, the RTL code. The pivotal act was Alibaba's T-Head division releasing its verified, high-performance RISC-V cores as completely free, open-source products.

In Part II, we argue this created a "second-level de facto standard" systematically dismantling the Western commercial model. T-Head's strategy is a "killer viral product" where the product is free.
Progressing from the C906 to the out-of-order C910 and C920, T-Head provided fully verified cores with complete SDKs, optimized toolchains, simulators, debuggers, and Linux-capable software. Zero-dollar adoption with minimized engineering risk created overwhelming convenience no academic project could match. While the ISA spec allows infinite variation, the gravitational pull of a zero-cost, verified core is inescapable. Companies download the core, wrap proprietary logic around it, and go, standardizing T-Head's bus protocols, interrupt, and debug architectures.

Herein lies the tragedy for Western RISC-V players. SiFive, Andes, and Codasip, having invested hundreds of millions, cannot compete against a high-end core offered without financial or legal strings, an economic mismatch of monumental proportions, a disconnect between the Western view of RTL as private capital and China's model treating foundational IP as digital public infrastructure.
The industrial response within China has been viral scaling: hundreds of fabless companies integrating T-Head cores into SoCs for smart speakers, facial recognition, robotics, and electric vehicles, all rooted in a second-level standard whose roadmap Chinese entities define. This strategy now targets the architecture of artificial intelligence itself.

In Part III, we detail advanced RISC-V architectures derived from T-Head's free models, presenting SoCs like the D1, TH1750, A210, and the SG2042/SG2044. The culmination is SpacemiT's K3, the first commercial RISC-V chip that is out-of-order, Linux-compatible, and RVA23-profile compliant, integrating CPU and AI acceleration and already in mass production.